In order to function, integrated circuits of semiconductor dies must be in electrical communication with signal input and output connections as well as with power, ground, or bias connections, which are external to the integrated circuit. For example, power and ground, or other reference voltages must be supplied for operation of the integrated circuit. Additional connections used for input, output and timing signals may also be required. These connections are conventionally made through leads or other conductive elements connected to bond pads associated with a semiconductor die.
As electronic devices have become smaller and more sophisticated, the challenge of minimizing the space used by component electrical circuits and connections on a semiconductor die has continued to increase. One technique for reducing the amount of space occupied by electrical circuits and connections required by a semiconductor die is the use of through wafer interconnect (TWI) vias to be formed through the entire thickness of a semiconductor die between the active surface and backside thereof, allowing electrical connection by “via studs” through the semiconductor die. This allows the external electrical elements of a semiconductor die to be more compact and also allows a die to be stacked with other devices to reduce the footprint space required by the die.
Another technique for reducing the space required by a semiconductor die includes the use of a redistribution layer (RDL), which is an additional level of wiring to reposition bond pads providing inputs and outputs for the die. The redistribution layer may be used to reposition bond pads from the perimeter or along the centerline of a semiconductor die to alternative locations, which may be less crowded.
In a conventional method of forming a backside redistribution layer, a backside of a substrate is thinned to expose a conductive via stud and a first dielectric layer is formed over the backside of the substrate. A first photolithography step is used to remove the dielectric material from over the via stud. Next, a metal layer is formed on the first dielectric layer and in electrical contact with the via stud. The metal layer is then patterned using a second photolithography step and a wet etching step so as to form a bond pad in contact with a via stud, a bond pad located away from the via stud and a conductive trace electrically connecting the bond pads. A second dielectric layer is then formed over the bond pads, the trace, and the first dielectric layer. The second dielectric layer is then removed from over the bond pad located away from the via stud using a third photolithography step.
Because photolithography is substantially expensive, the large number of photolithography steps used in the conventional process to form a redistribution layer increases the overall cost of the manufacture. Furthermore, the use of a wet metal etch to etch the metal layer may lead to undercutting along with an undesirable curved metal profile. Accordingly, there is a need and desire for a better method of forming a redistribution layer.